NeditekMastering p-GaN HEMT Symbol & Transistor Structure
p-GaN HEMT is a 1 enhancement-mode power transistor. Its core gameplay is to use the positively doped gallium nitride gate layer to deplete the underlying two-dimensional electron gas (2DEG) channel, thus achieving a safe and reliable “normally off” state under 0V bias. If you look closely at its schematic symbols, you will find that the body diode that comes standard with traditional MOSFETs has been deliberately removed. These details not only directly indicate that the reverse recovery charge (Qrr) of the device is zero, but also mark a complete reversal of the underlying physical circuit characteristics.
If you follow the old habit of drawing schematics of silicon-based devices and apply them to these wide band-stop devices, you will definitely have to follow suit. Many engineers directly used the traditional silicon tube gate drive rules to design the design, but the parasitic oscillations they did not notice directly burned the p-GaN gate. In the next technical disassembly, we will dig deep into the underlying transistor structure that determines this high-frequency characteristic and tell you: to truly master the ultra-high efficiency of gallium nitride power tubes, we must stick to the iron laws when drawing schematics.
S.C.G. Architecture Rules: Deciphering the Internal Structure of Gallium Nitride Transistors
Substrate And Epitaxy: Laying A Solid Foundation
The substrate directly determines the size of the heat dissipation ceiling and parasitic capacitance of the device. Major manufacturers typically grow an aluminum nitride (AlN) nucleation layer on a standard silicon (Si) or silicon carbide (SiC) substrate. This buffer layer perfectly absorbs the severe lattice mismatch between silicon and gallium nitride, preventing physical crystal defects from propagating all the way up to the top core switching region.
Channel: Naturally Formed 2DEG
At the interface of the gallium nitride layer and the AlGaN barrier layer, a so-called “two-dimensional electron gas (2DEG)” is naturally formed “. The piezoelectric polarization effect will force electrons into microscopic quantum wells, making a superconducting channel with ultra-high electron mobility. This inherent conductivity means that the most primitive GaN HEMTs are actually depleted (I. e., “normally on”). If this thing is used directly in the power inverter, in case the gate driver accidentally loses power, the system will immediately face the risk of a devastating short circuit.
P-GaN Grid: Forced To “Enhanced”
In order to solve the hidden danger of “normally on”, the device introduces a p-GaN layer as a built-in voltage barrier to actively “drain” the electrons in the 2DEG channel below “. By precisely growing a layer of p-doped gallium nitride in the gate area, the energy level can be pulled up and the electron flow can be completely cut off at 0V, at which time the tube becomes a “normally off” state (I. e. enhanced, e-mode). When you add a forward voltage to the gate (usually 5V), this depletion effect is canceled out, the 2DEG reconverges, and a huge current can travel smoothly between the drain and the source.
Analyzing GaN HEMT Symbols in Schematic
When building the principle library, standardizing the symbols of GaN HEMT can effectively avoid those catastrophic routing errors in the PCB layout stage. This visual symbol must allow Layout engineers to see through the distinctive physical characteristics of the device at a glance.
The Missing Body Diode Represents Zero Qrr
In the official p-GaN schematic symbol, the parallel intrinsic diode common to silicon tubes is completely removed. The reverse current of the gallium nitride transistor goes directly to the 2DEG channel, and does not rely on the p-n junction composed of minority carriers. Because of this, in the mathematical sense, its reverse recovery charge (Qrr) is purely zero. Hard switch topologies such as totem-pole PFC(Totem-Pole PFC) eat this feature. Only in this way can the risk of bridge arm straight-through frying machine be completely eliminated.
Harsh EDA Tool Drawing Specification
When engineers draw symbols, they must clearly distinguish between the main power source (Power Source) and the Kelvin source (Kelvin Source). When the UHF di/dt switch switches, the parasitic inductance on the source pin will produce a very significant voltage drop. A qualified GaN HEMT symbol will definitely be equipped with a dedicated fourth pin (Kelwen source). It cleverly avoids the main power current loop, ensuring that the gate drive signal can be returned to the core p-GaN layer with extreme precision.
Gallium Nitride Transistors vs. Traditional MOSFETs: Hard-core Engineering Reality
To evaluate the difference between the two, you have to step outside the marketing rhetoric of the manufacturer Datasheet and dig deep into the underlying physical conduction mechanism.
The Third Quadrant Of Subverting “Dead Time” Logic Turns On
During the dead time of the half-bridge switching cycle, the reverse voltage drop (VSD) of the gallium nitride device is much larger than that of conventional silicon-based MOSFETs. Since there is no body diode, its reverse on voltage is actually equal to “gate off voltage + device threshold voltage (Vth)”. Compressing the dead time to 2ns can significantly reduce the on-loss. If we continue to follow the old habit of making silicon tubes and insist on leaving a dead time of 50ns, it will simply be a waste of money and heat in the gallium nitride channel, completely destroying the efficiency advantages brought by the wide bandgap technology.
GaN HEMT vs Si Superjunction MOSFET
| Parameter | Si MOSFET | p-GaN HEMT |
| Gate Threshold Voltage (V_th) | ~3.0V to 5.0V | ~1.5V (Typically 1.2V to 2.0V) |
| Qrr (Reverse Recovery Charge) | High (Due to minority carrier body diode) | Zero (0 nC, no minority carriers) |
| Third Quadrant V_SD | ~0.8V to 1.2V (Body diode forward voltage) | V_off + V_th (Higher, typically 1.5V to 2.5V) |
| Typical Gate Drive Voltage | 10V to 15V | 5.0V to 5.5V (Strict maximum < 7V) |
Expert Case Study: 7V Gate Overvoltage Trap
The absolute maximum rated voltage of the p-GaN HEMT gate is usually below 7V, which is a red line that cannot be touched. If you make a design plan to save trouble and directly use the standard 12V MOSFET driver that used to push the silicon tube, the gate of the p-GaN will definitely be broken down instantly, and there is no room for saving.
Tell me about the blood pit that our team really stepped on. At the end of last year, we were struggling to 1 a 3kW high-power AI server power supply. At that time, when adjusting the totem pole PFC stage, the discrete gallium nitride tubes on the board were just like hanging whips. 1 they were pulled full load, they would explode the machine without warning, and the scrap rate was maddening. Later, the hardware veterans in the group held a high-frequency oscilloscope probe to stare at the waveform, and finally caught the current: on the nominal 5V gate on signal, a high-frequency ringing spike as high as 3.5V was strangely superimposed.
After searching for it, the culprit was actually a PCB trace that had gone a little far. The parasitic inductance of the wiring in this area, which is about 3nH, collided with the input capacitance (Ciss) of the tube itself, causing high-frequency resonance, which abruptly pushed the gate voltage up to 8.5V in just 12 nanoseconds. Although this is only a nanosecond overvoltage, it will forcibly “pour” holes into the p-GaN layer, resulting in irreversible permanent drift of the threshold voltage of the tube. The final result is that the die is directly short-circuited and violently killed.
After that painful lesson, we have set two iron laws that no one can break. If we want to not blow up the plane, we must stick to them:
First, don’t worry about the cost of components. You must be honest with the high-precision LDO and clamp the gate drive power supply in the safety zone of 5.0V to 5.5V.
Second, the Layout route must be cut to the extreme. The absolute physical distance from the driver IC to the HEMT gate pin must not exceed 5mm. If the board space is too crowded to be distributed, then simply bite your teeth in one step and directly replace the monolithic integrated gallium nitride power IC (that is, the driver and the power tube are made on the same wafer) to completely “uproot” this troublesome routing inductance circuit from the physical level “.
Technical Q & A (Common Demining Guide)
Why Does A P-GaN HEMT Not Have A Body Diode?
Because it is built by lateral heterojunction (AlGaN/GaN), it is not a vertical p-n junction at all. When the drain voltage is lower than the source voltage, the reverse current goes directly to the native 2DEG channel. Since there are no minority carriers involved, the reverse recovery charge (Qrr) is naturally zero.
How Do You Use A Conventional Multimeter To Test A P-GaN Transistor?
You have to be very careful with a multimeter to measure this thing. The test voltage provided by the ordinary multimeter in the diode position is not fixed. When measuring in the forward direction (drain to source), the resistance is infinite; when measuring in the reverse direction (source to drain), you will see a voltage drop of about 1.5V to 2V. Remember: this is actually the conduction voltage drop of 2DEG in the third quadrant. It is not a real diode at all.
What Is The Functional Difference Between The D-Mode And E-Mode Of GaN HEMT?
D-mode (depletion type) is normally open at 0V, and a negative pressure (such as -15V) must be given to completely shut down. E-mode (enhanced), specifically p-GaN devices, are normally off at 0V and require a positive bias (usually 5V) to turn on. For the absolute safety of the power supply system, the mainstream of the industry is E-mode.
Why Does The P-GaN Gate Voltage Have To Be Deadlocked Below 7V?
The p-type gallium nitride layer acts like a Schottky contact, unlike a thick silicon dioxide insulating layer like a traditional silicon tube. Once the gate voltage crosses the warning line of 7V, it will trigger hole injection into the device barrier, which not only disturbs the internal electric field, but also causes irreversible threshold voltage instability.
Can I Use A Normal Silicon MOSFET Driver To Push P-GaN HEMT?
Absolutely not. Ordinary silicon tube driver can output a voltage of 10V to 15V casually, and the p-GaN grid will be directly broken down as soon as it is powered on. You must have a special GaN driver, which can not only accurately clamp the output voltage to 5V, but also have sub-nanosecond transmission delay, so as to match the horrible switching speed of GaN exceeding 100V/ns.